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This paper proposes HSTL based energy efficient design of frame buffer for a digital image processor. Our aim is to make energy efficient frame buffer design and for that reason we are using different types of HSTL IO standards. This design is implemented on both Virtex-6 FPGA and Airtex-7 FPGA and compared the power dissipation. It is observed that at 1GHz operating frequency, there is maximum IO...
A fast intra mode decision algorithm for H.264/AVC is proposed in this paper. The objective is to reduce the encoder complexity without significant rate-distortion performance degradation. Three methods are adopted: (1) the block size is selected between 4times4 block and 16times16 block based on the smoothness and correlation information. (2) A characteristic is also exploited, which is using to...
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