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Implementing floating-point (FP) Fast Fourier Transforms (FFT) on Field Programmable Gate Arrays (FPGAs) still represents a challenging task. The limited resources on target devices coupled with the inherent complexity of the FFT are among factors limiting widespread utilization. This paper presents the design of a scalable, FP FFT core for synthesis on Xilinx FPGAs. Its architecture uses a radix-2...
This paper presents a modified pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture. The canonic signed digit (CSD) representation is used to design the function of complex multiplier, which is the main function block in the FFT processor. The processor of a 16-bit 16-point pipeline FFT is realized on the Xilinx Virtex-4 FPGAs. The achieved maximum clock frequency is...
Efficient architectures for realizing MDCT/IMDCT are presented. Based on the symmetry property of trigonometric functions, N-point MDCT formula was transferred into an odd-even index paralleling process which can be achieved by two different types of decomposition, recursive formed DCT-II kernel or FFT-based DCT-IV kernel. Then a butterfly unit is employed to accelerate the computational speed. Furthermore,...
FFT algorithm is the popular software design for spectrum analyzer, but doesnpsilat work well for parallel hardware system due to complex calculation and huge memory requirement. Observing the key components of a spectrum analyzer are the intensities for respective frequencies, we propose a Goertzel algorithm to directly extract the intensity factors for respective frequency components in the input...
Fast Fourier Transform (FFT) is the most basic and essential part of Software Defined Radio (SDR). Therefore, designing regular, reconfigurable, modular and low hardware complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like DCT, DST etc. In this paper, the authors analyze...
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