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This paper presents a flexible-reach 0.5–16.3 Gb/s serial transceiver which is integrated into a field-programmable gate array (FPGA) and fabricated in 16-nm FinFET CMOS. The transceiver is fully adaptive to cover the FPGA requirement to support a multitude of combinations of data-rates and standards such as 10 G-KR, PCIe Gen3/4, and SFP+ across a wide range of channel loss profiles. High-performance...
The sample and hold circuit is perhaps the most important building block in most data acquisition systems such as data converter. Flexibility of this block can be used to improve the whole performance of the system. In this work a flexible structure with variable gain is presented. The circuit is used to calibrate a typical time interleaved analog to digital converter. Simulation results indicated...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
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