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The design and implementation details of a 4-bit time interleaved successive approximation register (SAR) analog to digital converter (ADC) for UWB application is presented in this paper. Low latency SAR ADC has been implemented by detecting two bits per clock cycle. Major contribution of this paper is that it uses only two capacitive DACs instead of three capacitive DACs. This is achieved by using...
A digital calibration technique is proposed for DAC mismatches in delta-sigma (DeltaSigma) modulators. The delta-sigma modulator works as an incremental ADC in the calibration mode. The DAC mismatches are found by solving linear equations and are compensated digitally. The technique can be used in double-sampling delta-sigma modulators as well.
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
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