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The existence of multiple copies of the same functional units in a design allows on-line testing to be performed by comparing the output responses of identical circuits when identical input sequences are applied to them. We extend the output response comparison scheme for identical sequential circuits in order to increase the fault coverage and reduce the fault latency of an unknown input sequence...
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
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