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Static timing analysis (STA), which is a part of design automation requires the generation and storage of delay values for combinational standard cells and the setup and hold time values for sequential cells at numerous corners in the form of a Look Up Table (LUT). This paper proposes a novel approach for LUT generation of sequential standard cells by developing a model for the setup time. The model...
The designer sometimes wants to insert register(s) in specific location(s) of a design in order to break critical paths. To do so, the designer has to manually insert registers in all parallel paths as well to balance registers in all paths to keep the functionality of the design intact. This task is known as ‘register balancing’ in the design community. The design size, complexity and hierarchy make...
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