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A 3 MHz-to-1.8 GHz, 94 -to-9.5 mW, all-digital delay-locked loop (ADDLL) using 65-nm CMOS technology is presented. In this paper, a cyclic half-delay-line architecture that uses the same type of delay lines for cyclic delay determination and coarse locking is proposed and used to achieve the design goals of small footprint and fast locking for a large operating frequency range. In addition,...
The Clock gating reduces dynamic power dissipation in synchronous circuits. The gating function is the process of filtering glitches from a block which is achieved by inserting clock gating cell. Clock gating logic uses strong and weak matching process, they are two kinds of factor form matching. The strong matching seeks for the matches which are externally present in the factored forms and the weak...
Sink mobility has become an increasingly important requirement of various sensor network applications. Handling such mobile sink conditions brings new challenges to large-scale sensor networking. This investigation proposed a hybrid-structure routing protocol (HSRP) that combines the benefits of grid-based and cluster-based structures. Grid-based structure is designed to solve the cluster head selection...
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