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High speed content addressable memory design has high speed search function in a single clock. Parallel match line is used to compare. In robust Low power sense amplifier and high speed are highly sought-after in CAM designs. The value is given to search engine and its finds the value where its present. In the existing parity bit is introduced that leads to delay reduction at a cost of less than area...
This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC scheme uses two dummy rows for digitally adjusting the pulse width and the delay of the sense amplifier enable signals of the CAM without disturbing the normal operation. Therefore,...
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