Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
4×4 Vedic multiplier using domino logic is proposed in this paper. The designs are implemented in GPDK 90nm technology on cadence virtuoso tool using spectre simulator. Multiplication is a fundamental operation, which is widely used in many digital signal processing systems, multimedia applications, computers and many digital systems. Power and delay are two important design constraints but there...
In this work, an efficient implementation of a programmable Finite Impulse Response (FIR) filter based on the use of the Karatsuba Multiplication Algorithm (KMA) is presented. In this FIR filter circuit, a parallel, Modified Booth (MB) pre-encoded, Carry-Save (CS) Wallace tree multiplier is used as a building block. The KMA is a fast divide and conquer algorithm for the multiplication of large numbers...
This paper comprises of new low power multiplication algorithm and VLSI architecture. The one less than previous is foundation to built the proposed algorithm. The algorithm is simple straightforward to find NxN unsigned binary number multiplication using 2n-1 constant number which is used recursively for both multiplicand and multiplier. It revealed that reusability of the hardware resource results...
In network-on-chips (NoCs), how to reduce the power consumption of router buffers has been a major concern. In this paper, we propose a methodology to minimize the power consumption of routers with meeting all the deadlines of traffic flows. First, we present a network calculus-based method to analyze the worst-case delay of each flow in NoC. By using the method, an active buffer sizing algorithm...
Montgomery modular multiplication is widely used in public key cryptosystems. This paper presents an energy-efficient architecture for word-based Montgomery modular multiplication algorithm. Using the proposed architecture mapping scheme in dependency graph, the switching activity of kernel can be greatly reduced. In addition, the proposed design also retains one-cycle latency between neighboring...
A diagnosis technique based on delay testing has been developed to map the severity of process variation on each cell/interconnect delay. Given this information, we demonstrate a post-silicon tuning method on row voltage supplies (inside a chip) to restore the performance of failed chips. The method uses the performance map to set voltages by either pumping up the voltage on cells with worse delays...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.