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Power consumption is a big challenge in chip design. Decisions taken in early design phases have large impact on the power consumption. Generally, simulation-based Design Space Exploration (DSE) is computationally costly for large problems due the size of design space. Simulate the possible scenarios in a distributed fashion can decrease the time to find efficient solutions. In this paper we describe...
This paper forwards a neural network based VLSI power estimation Simulator (NBPE) for VLSI specification design with a graphical user interface developed. The user can enter parameters from VLSI specification such as IO number, frequency, flash depth and parameters on neural network structure such as layer number, learning algorithm etc. This simulator then estimate VLSI's power based on given information...
This paper forwards a neural network based VLSI power estimation on VLSI chip specification. This paper used neural network to perform VLSI power estimation. Experiments were made on chip specification parameters extracted from the datasheet of TI series micro-controllers. Different net structure, training plans and vector organizations were applied. Based on limited number of test vector, experimental...
This paper introduces a modeling and simulation technique that extends transaction-level modeling (TLM) to support multi-accuracy models and power estimation. This approach provides different combinations of power and performance models, and the switching of model accuracy during simulation, allowing the designer to trade off between simulation accuracy and speed at runtime. This is particularly useful...
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