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In this paper, a new peak hold circuit which detects the top value and the bottom value of the power supply noise of a VLSI circuit is proposed. We can make a noise map by distributing the circuit over the chip and find hot-spots in which large power supply noise occurs. This circuit needs no extra clean power supply or external clock signal. Also, low power consumption can be expected because it...
This paper proposes a Cascaded H-bridge Multilevel Inverter (CHMI) based pulsed power supply for the sterilization of liquid foods using Pulsed Electric Field (PEF). The utilization of a CHMI allows the system to reach high voltage without the use of transformers while fulfilling the pulse requirements for effective liquid food sterilization. By using the CHMI topology, no extra clamping diodes or...
Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
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