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This paper describes the design and realization of a low-voltage low-power RF variable gain amplifier in a 0.18 um CMOS technology. The proposed amplifier employs an active negative feedback technique to achieve wide bandwidth operation. Simulation results showed that the proposed circuit could achieve 1.78-GHz bandwidth with 13.04-dB gain under a single 1-V power supply voltage, while draining current...
This paper presents the design and integration of a fully-integrated dual-conversion zero-IF2 CMOS transceiver for 9-band MB-OFDM UWB systems from 3.1 GHz to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single combined mixer for both RF down-conversion in RX and up-conversion in TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated...
A single-ended wideband low noise amplifier (LNA) for GSM (DCS1800, PCS1900) and WCDMA (Band I to IV) were designed and implemented using 0.18 mum CMOS technology. The circuit topology is based on inductively-degenerated common-source (IDCS) using on-chip inductors at the input circuit for input matching and shunt-peaking components for bandwidth enhancement at load tank. Post layout simulation results...
In this paper we discuss a CMOS based wideband VGA configuration designed in 0.18 mum UMC process providing a gain of 21 dB and bandwidth of 360 MHz with control voltage range of 1.0 V to 1.6 V. The results of the design were verified through layout. Further, the design was modified to incorporate it in an AGC for Software radio applications. The design process resulted in two ultra wideband VGA designs...
This paper presents an inductorless 0.1-1 GHz automatic gain control (AGC) circuit comprised of a variable gain amplifier (VGA), power detector (PD), and comparator. The VGA has a gain control range of -28~23 dB with a 1 GHz 3-dB gain bandwidth using a cascode amplifier with negative capacitance. The PD shows an input power range of -30~20 dBm using an improved unbalanced source coupled pair, which...
A fully integrated 1.175 to 2 GHz differentially tuned frequency synthesizer aimed for DVB-T tuners is implemented in 0.18-mum CMOS. Techniques are proposed to make the loop bandwidth constant across the whole output frequency range to maintain phase noise optimization and loop stability. It exhibits in-band phase noise of -97.6 dBc/Hz at 10 kHz offset and integrated phase error of 0.63deg from 100...
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