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Scan architectures with compression support have remedied the test time and data volume problems of today's sizable designs. On-chip compression of responses enables the transmission of a reduced volume signature information to the ATE, delivering test data volume savings, while it engenders the challenge of retaining test quality. In particular, unknown bits (x's) in responses corrupt other response...
Multi-gate-length (MGL) and dual-gate-length (DGL) biasing techniques are investigated for timing constraint-aware active mode leakage power reduction of VLSI circuits. Key design and technology characteristics essential for leakage reduction are identified and utilized to carry out a Monte-Carlo-based study to benchmark MGL against DGL over different design styles and various technologies. Extensive...
Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
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