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Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. To improve switching performance, energy/switching, and also the robustness of the subthreshold logic for the implementation of 1-bit static full adder, we propose the use of sub-FinFET (sub-threshold voltage FinFET) transistors. The power, speed and energy evaluation has...
The design of high speed, compact and low power priority encoder circuits using static CMOS gates is presented. The proposed hierarchical static design has improved delay and power compared to a dynamic domino circuit implementation. For an 8-bit priority encoder design the proposed approach shows 77.1% power dissipation, 63.6% transistor count and 36% delay improvement. The improvement increases...
Elimination of the p-MOS transistor from the pass gate network significantly reduces the parasitic capacitances associated with each node in the circuit, thus, the operation speed is typically higher as compared to the CMOS counterpart. But then the improvement in the transient characteristics comes at the price of increased process complexity. In Complementary pass transistor logic (CPL) circuit,...
In recent years, low power design has become one of the main focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, where efforts are taken to reduce subthreshold leakage, operation of digital circuits in the subthreshold region, utilizes this current, minimizing...
This paper presents a new study over logics circuit operation in subthreshold and threshold region. CMOS circuit model operation logic will make deep primary reference for this study. This new research presses low voltage features to circuit stated. By using profoundest results of the study, we will develop FFT processor designs as an example of digital wireless circuits. The FFT processor can operate...
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division, address calculation, ..Etc. In this paper we have presented study of different logic structure using 1-bit full adder...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
We present a technique, termed clock-generating (CG) domino, for improving dual-output domino logic that reduces area, clock load and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits indicate an average reduction in area, clock load, and power...
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