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In this paper, we propose a new method to generate vectors for post-silicon delay characterization, especially for exposing delay marginalities during post-silicon validation and speed binning during testing. Our method generates vectors that are guaranteed to excite the worst-case delays of fabricated chips without introducing any pessimism. It embodies several innovations, including a resilient...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
In this paper, we propose a robust STBC transmission scheme to combat the timing synchronization errors over frequency-selective multiple-access channels. First, the equivalent channel model in the presence of timing synchronization errors is derived and we find that the synchronization errors result in an equivalent channel model with larger number of correlated channel taps. Based on this correlated...
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