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Higher sensing margin and longer retention time are critical issues for commercializing 1T DRAM. In this paper, we propose a body-raised double-gate structure to improve sensing margin and retention time of 1T DRAM and confirm the improvements through 3D simulation. This structure shows about 20% higher sensing margin than the planar structure. We have achieved longer retention time by using high...
In this work we propose a unified model for the low-field effective electron mobility in SOI and DG-MOSFETs with ultrathin SiO2/HfO2 gate stacks, different substrate and channel orientations and uniaxial stress conditions.The model accounts for quantum-confinement effects in the MOSFET channel. Next, we apply this mobility model to a 1D quantum drift-diffusion (QDD) transport model in order to investigate...
Ultra Thin Body Si-On-ONO (UTB SOONO) transistors with ultra thin spacer are successfully demonstrated and evaluated. They have shown increased driving current more than 30% compared with conventional UTB SOONO transistors with thick spacer due to reduced source/drain resistance without short channel effect degradation by using thin spacer. In this paper, it is shown that thin spacer technology is...
A scaled, undoped, thin-BOX, planar FBC technology is demonstrated for the first time, featuring 10-nm BOX, 25-nm SOI, high-k, metal gate, separate back-gate (BG) doping, and raised source-drain epitaxy. Retention of a minimum 3-muA sensing window for 100 ms, in devices with 60-nm gate-length (Lg) and 70-nm diffusion width (W), represents the best retention time of all sub-100-nm FBC devices. FBC...
For the first time, ultra low IOFF (16.5 pA/mum) and high IONN,P (2.27 mA/mum and 1.32 mA/mum) currents are obtained with a multi-channel CMOSFET (MCFET) architecture on SOI with a metal/high-K gate stack. This leads to the best ION/IOFF ratios ever reported: 1.4 times 108 (0.8 times 108) for 50 nm n- (p-) MCFETs. We show, based on specifically developed integration process, characterization methods...
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