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The performance and threshold-voltage variability of vertical SOI FinFETs are compared against those of planar fully depleted SOI MOSFETs with thin buried oxide, via three-dimensional device simulation with atomistic doping profiles and gate line-edge roughness, for the 22 nm CMOS technology node (25 nm gate length). Compact modeling is then used to estimate six-transistor SRAM cell performance metrics...
In this work we propose a unified model for the low-field effective electron mobility in SOI and DG-MOSFETs with ultrathin SiO2/HfO2 gate stacks, different substrate and channel orientations and uniaxial stress conditions.The model accounts for quantum-confinement effects in the MOSFET channel. Next, we apply this mobility model to a 1D quantum drift-diffusion (QDD) transport model in order to investigate...
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