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NBTI imposes a challenge for the design of circuits in DSM technologies. NBTI causes increase of Vt of the PMOS transistors, thus leading to timing degradation of CMOS circuits over time. This manuscript presents a NBTI-aware transistor sizing technique for high-performance CMOS gates, which improves the cell reliability with minimum area penalty. The delay of an inverter designed on a 32 nm technology...
The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies, and...
This paper presents a design methodology incorporating multi-threshold CMOS (MTCMOS) into delay-insensitive asynchronous circuits in order to solve the problems of the synchronous counterpart, e.g., sleep signal generation, storage element data loss during sleep mode, and sleep transistor sizing. Significant leakage power reduction has been demonstrated by simulation. Due to the flexible timing requirement...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
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