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Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay identify multi-cycle paths (MCPs), which allow timing to be relaxed, but ignore the set of reachable states, achieving scalability at the cost of a severe lack of precision. Even simple circuits contain paths affecting timing...
Although QCA (quantum dot cellular automata) has been introduced as a new kind of technology for over a decade, it still continues to be so and its merits and flaws are yet under study for future practical use. One of the problems of this technology is the dependency of its circuit timing to its layout. An asynchronous design methodology for QCA has been offered to solve this problem. The proposed...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
It has been shown that several process parameters encounter variation in the DSM era. Consequently, several techniques, such as statistical gate sizing and clock skew scheduling, have been proposed to enhance yield loss. In this work, we propose an integrated statistical framework for gate sizing and skew scheduling in order to minimize yield loss and area cost. While traditional separate methods...
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