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In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). While this technique offers great dynamic power savings mainly in array multipliers, due to their regular interconnection scheme, it misses the reduced...
In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low dynamic power consumption...
Low power and high speed requirement is a challenging task in design of ALUs. Supply voltage scaling is promising approach because it reduces switching activities and active power but it degrades the performance and robustness. Recently a new like static circuit family called Feedback-Switch Logic (FSL) has been proposed. FSL is suitable for high speed and low power because it offers fast switching,...
Based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier, a low-power multiplier design with row and column bypassing is proposed. Compared with the row-bypassing multiplier, the column-bypassing multipliers and the 2D bypass multiplier for 20 tested examples, the experimental results show that our proposed multiplier reduces 25.7% of the...
Decimal multiplication is an integral part of financial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area...
The paper presents a novel high speed and low power 15-4 Compressor for high speed and low power multiplication applications. The proposed compressor uses bit sliced adder architecture to exploit the parallelism in the computation of sum of 15 input bits by five full adders. The newly proposed compressor is also centered around the design of a novel 5-3 compressor that attempts to minimize the stage...
In this paper the authors introduce a novel experimental method when using genetic algorithms (GAs) to design and optimise digital hardware (HW). This approach proved to enhance the GA's performance. It produced more design solutions than selected comparable techniques used by others and maximises optimisation. The novel aspect of our algorithm works at the fitness evaluation stage, where every single...
Montgomery algorithm is widely used in public-key cryptographic algorithms. In this paper, a improved CSA is used to remove the carry chain while implementing Montgomery algorithm. It has a shorter delay. To eliminate the signal's global broadcasting, the algorithm is mapped to a systolic array. The RSA encryption/decryption chip is implemented by the modular multiplier based on Montgomery systolic...
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