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Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix...
Logical elements with Single-Event Transients Compensation were simulated on the base of the bulk 28-nm CMOS design rule. The result of an impact of a single nuclear particle on MOS logical gate is a noise pulse, being a single-event transient. The combinational logic of error decoder can prevent all noise pulse propagating through NAND and NOR gates for the output state null “0” of bits error decoder...
RAM decoders were simulated on base the bulk CMOS 28-nm design rule. The result of a single nuclear particle impact on a MOS logical gate is a noise pulse as a single-event transient. The internal error decoder gives the main contribution to a noise sensibility of a RAM decoder. The combinational logic of error decoder can prevent all noise pulse propagating through NAND and NOR gates for the output...
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