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An Ultra Low Power (ULP) biomedical System-on Chip (SoC) has been developed for efficient ECG/EEG signal processing in a Body Area Network environment. This experimental SoC explores the use of event-driven peripheral modules that autonomously interact with external sensors together with the use of an Application-Specific-Instruction-set Processor (ASIP) to optimize energy-efficiency during active...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
In this paper, a 12-bit 50MHz Pipelined Low-Voltage ADC is presented, which consists of 8-stage-pipelined low resolution ADCs and a 4-bit flash ADC. Several critical technologies are used to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, gain-boosted telescopic OTA and so on. Finally the whole system is taped out in SMIC...
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