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This paper presents a novel switching scheme for an ultra-low energy charge-redistribution digital-to-analog converter (DAC) to be used in successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed scheme employs unit capacitors for voltage sampling and charge redistribution. Compared with previously published capacitive DAC which uses the same unit size of capacitor array,...
An integrated digitally-controlled crystal oscillator (DCXO) is presented that generates both 38.4 MHz and also a 32.768 kHz real time clock (RTC) from a single 38.4 MHz crystal. The DCXO can startup independently and transition seamlessly in and out of software control. The tuning range is 280 ppm with 2 ppb/step and guaranteed monotonicity. The phase noise is -135 dBc/Hz at 1kHz offset and -146...
An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation (SA) analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 μm digital process is presented. To overcome the input sampling switches limitation imposed by the low supply voltage we make use of a track-and-hold circuit based on a low-voltage, low-stress and reliable clock signal with a...
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