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Firstly an embedded 55-nm Flash design based on split-gate Flash bitcell is proposed by 32KX64 IP. It demonstrates competitive features for production by wide voltage supply range (VDD=0.86~1.32V, and VD25=1.6~3.6V), low-power read feature (96uA/MHz, 64 bits), fast wake-up time from power off (<; 2us), and fast operation read speed up to 75MHz (VDD=1.08V).
We present industry's smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The cell is aggressively scaled at 58% (vs. 45nm) and features the key innovation of High-K Metal (HK/M) stack in the Deep Trench (DT) capacitor. This has enabled 25% higher capacitance and 70% lower resistance compared to conventional...
A high performance embedded DRAM with deep trench capacitor and high performance SOI logic has been deployed in 45nm and 32nm technology nodes. Following a yield ramp of the sub-2ns latency 45nm technology, we present, for the first time, a 32nm eDRAM technology fully compatible with high performance logic with high-?? metal gate access transistor and high-?? node dielectric for the deep trench storage...
Floating-gate transistors that have contacts to the lowest metal to the polysilicon floating-gate were fabricated to determine if the lowest metal flow alone could normalize charge across multiple floating gates. The metal contacts did not normalize charge for different numbers of contacts to polysilicon; however, a decreased variance of trapped charge was found when compared to polysilicon floating-gates...
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