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This paper presents a high performance THz imaging array using advanced CMOS technology. The single element of the 0.3 THz 4×4 45 nm CMOS imaging array is composed of a high-efficiency differential on-chip antenna meeting all metal-density rules, which is coupled to a differential detector and a low noise CMOS IF amplifier. The array results in an NEP of 100 pW/Hz1/2, a responsivity of 1.8–2.0 kV/W...
A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to...
An 820-GHz 8×8 imaging array using diode-connected NMOS transistor detectors is demonstrated in 130-nm CMOS process. Measured mean responsivity of 3.4 kV/W and mean NEP of 28 pW/Hz1/2 at 1MHz modulation frequency are achieved. The NEP is 3.5X lower than that of NMOS and slightly lower than that of Schottky diode terahertz imaging arrays implemented in CMOS. The minimum NEP is 15.5 pW/Hz1/2, which...
This paper proposes a CMOS 6 bit A/D converter with input voltage range detectors based upon folding amplifier with a folded-cascode load. The input voltage range detectors allow the proposed A/D converter to reduce the power dissipation by turning on one fourth of all the comparators. The measurement result illustrates ENOB of 5.1 bits at 250Msps, power dissipation of 106mW, and FoM of 17.5pJ/steps.
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