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H.264 video coding standard is widely used due to the high compression rate and quality. H.264 decoders usually have pipeline architecture by a macroblock or a 4 × 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. We propose variable pipeline architecture for H.264 decoders for efficient...
In this paper, an H.264 video decoder based on the new TMS320DM6437 (DaVinci) DSP is described. In this work both, DMA and memory architecture of the processor are fully exploited to improve the decoder performance. Profiling tests have been carried out in simulation using digital TV streams and DVD transcoded sequences. Performance is 10% better than that of the same decoder based on a TMS320DM642...
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