The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The complexity of high performance digital systems has rapidly increased. When we design such systems in a system-on-chip (SoC), lots of predesigned intellectual properties (IPs) are integrated to build a system. To verify the functionality of such systems, conventional simulation methods take extremely long time and they have limited debugging capability due to the existence of many predesigned IPs...
This paper presents a design methodology for hardware/software (HW/SW) architecture design using ESL tools (Electronic System Level). From C++ descriptions, our design flow is able to generate hardware blocks running with a software part and all necessary codes to prototype the HW/SW system on Xilinx FPGAs. Therefore we use assistance of high level synthesis tools (Catapult C Synthesis), logic synthesis...
MPEG Reconfigurable Video Coding project aims at providing more flexible and easier solutions to specify video coders and decoders. Many contributions are devoted to the RVC-CAL language, the standard description language. There are also contributions about the general framework of this new model of video coding, and many CAL descriptions for video algorithms. However, RVC compliant implementations...
The Reconfigurable Video Coding (RVC) framework is a recent ISO standard aiming at providing a unified specification of MPEG video technology in the form of a library of components. The word “reconfigurable” evokes run-time instantiation of different decoders starting from an on-the-fly analysis of the input bitstream. In this paper we move a first step towards the definition of systematic procedures...
In this paper motion compensation IP core design based on SOPC technology is researched, which achieves the software hardware co-design method in video decoding to overcome the drawbacks of the software decoding and hardware decoding. The design of hardware modularization which is based on the motion compensation algorithm in MPEG-4 video decoding standard is completed by using verilog HDL language...
Design at the Electronic System-Level (ESL) tackles the increasing complexity of embedded systems by raising the level of abstraction in system specification and modeling. Aiming at an automated top-down synthesis flow, effective ESL design frameworks are needed in transforming and refining the highlevel design models until a satisfactory multi-processor system-on-chip (MPSoC) implementation is reached...
The elaboration of new and innovative systems such as MPSoC (Multiprocessor System on Chip) which are made up of multiple processors, memories and IPs lies on the designers to achieve a complex codesign work. Specific tools and methods are needed to cope with the increasing complexity of both algorithms and platforms. Our approach to design such systems is based on the usage of a high level of abstraction...
A System-on-Chip Design of VLD (Variable Length Decoder) in multi-standard video decoder is proposed in this paper. Our design supports all the popular video compression standards, e.g. MPEG-1, MPEG-2, MPEG-4, H.264, AVS, RealVideo. Benefit from its low power, the design is especially suitable for wearable multimedia applications. Simulation results show that the whole design takes an area of 1.04mm2,...
Pipelining has been applied in many area to improve performance by overlapping executions of computing stages. However, it is difficult to apply on H.264/AVC decoding in frame level, because the bitstreams are encoded with lots of dependencies and little parallelism is left to be explored. Even slice-level parallelism in H.264 is intuitive, because there is usually only one slice in a frame, it is...
For the problems that MPlayer encountered when decoding high definition video on the embedded platform of Intel's CE3100, a novel dual-core player is designed according to the features of CE3100. The dual-core player includes one soft core player based on software decoder and one hard core player based on hardware decoder. Then, a main control center is introduced in the front of the player. The control...
With the development of communication, digital video compression technology turns into one of the most flourishing realm. In this paper the author introduces an AVS decoder design based on a multimedia chip-platform. In order to obtain the optimal performance, the structure of decoder adopts parallel algorithm with the centre processer and the coprocessor. The performance of the decoder which is about...
In this paper, we have proposed an efficient hardware-assisted syntax decoding model for software-based video decoder. The proposed syntax decoding model is a generic model for different video codec standards. The syntax decoding process is divided into codec-dependent high-level syntax parser and generic entropy decoding engines. Currently, the design is implemented specifically for the support of...
In this paper we focus on the design methodology to propose a design that is more flexible than ASIC solution and more efficient than the processor-based solution for H.264 video decoder. We explore the memory access bandwidth requirement and different software/hardware partitions so as to propose a configurable architecture adopting a DEM (Data Exchange Mechanism) controller to fit the best tradeoff...
Recent research has shown that in mobile devices, energy efficiency of the total system does not scale at the same pace with the energy efficiency of the silicon. The reason has been attributed to overheads in software, and in the context of multi-media codecs a new approach has been proposed. In this approach hardware accelerators are scheduled quasi-statically thus decreasing the interfacing overhead...
This paper presents a case study on designing an MPEG4 decoder system using our system-level design toolkit named system builder. We start with a sequential specification of the MPEG4 decoder behavior and generate an FPGA implementation. In order to improve the performance, we refine the behavioral description based on the analysis result obtained by a profiler. Finally, we achieve over 15 fps performance...
An important share of the consumer electronics market is focused on devices capable of running multimedia applications, like audio and video decoders. In order to achieve the performance level demanded by these applications, it is important to develop specialized hardware IPs in order to cope with the most computational intensive parts. Nowadays, designers are facing the challenge of integrating several...
The paper reports on an attempt to implement a real-time hardware H.264 video decoder. The initial results of the project are presented, especially a customized RISC core and some digital modules, both of which have been implemented in Xilinx FPGA. The former has to serve as a host processor that supervises the latter, which speed up the essential decoding subtasks. The system is designed and tested...
In this paper, architecture with combination of software and hardware for AVS variable length code decoding is designed. Logical and feasible division between software and hardware for the system is presented. Under control of embedded CPU, the design can decode fixed length code, unsigned or signed k-th Exp-Golomb code and context-based adaptive2D-VLC (CA-2D-VLC) code. Furthermore, decoding flow...
In this paper, the DIgital SYstem-on-a-chip (SoC) platform-based Design ENvironmenT for shared memory multiple instructions multiple data (MIMD) architectures (DISYDENT) is used. The applicability of the Disydent design flow to systems in the multimedia domain is illustrated. Two case studies typical of multimedia domains will be considered in which the Disydent design-space exploration method is...
In this paper, a decoding IP core for audio video coding standard (AVS) was designed, which can support AVS JiZhun profile High-Definition video bit stream real-time decoding. System composing of the SOC design and control flow of decoding was described in detail. Logical and feasible division between software and hardware was presented on the basis of sufficient validity check. C reference model...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.