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The complexity of high performance digital systems has rapidly increased. When we design such systems in a system-on-chip (SoC), lots of predesigned intellectual properties (IPs) are integrated to build a system. To verify the functionality of such systems, conventional simulation methods take extremely long time and they have limited debugging capability due to the existence of many predesigned IPs...
In this paper motion compensation IP core design based on SOPC technology is researched, which achieves the software hardware co-design method in video decoding to overcome the drawbacks of the software decoding and hardware decoding. The design of hardware modularization which is based on the motion compensation algorithm in MPEG-4 video decoding standard is completed by using verilog HDL language...
The elaboration of new and innovative systems such as MPSoC (Multiprocessor System on Chip) which are made up of multiple processors, memories and IPs lies on the designers to achieve a complex codesign work. Specific tools and methods are needed to cope with the increasing complexity of both algorithms and platforms. Our approach to design such systems is based on the usage of a high level of abstraction...
In this paper we focus on the design methodology to propose a design that is more flexible than ASIC solution and more efficient than the processor-based solution for H.264 video decoder. We explore the memory access bandwidth requirement and different software/hardware partitions so as to propose a configurable architecture adopting a DEM (Data Exchange Mechanism) controller to fit the best tradeoff...
An important share of the consumer electronics market is focused on devices capable of running multimedia applications, like audio and video decoders. In order to achieve the performance level demanded by these applications, it is important to develop specialized hardware IPs in order to cope with the most computational intensive parts. Nowadays, designers are facing the challenge of integrating several...
In this paper, a decoding IP core for audio video coding standard (AVS) was designed, which can support AVS JiZhun profile High-Definition video bit stream real-time decoding. System composing of the SOC design and control flow of decoding was described in detail. Logical and feasible division between software and hardware was presented on the basis of sufficient validity check. C reference model...
In complex SoC design, the reusable IP is very useful to achieve the whole system with high verification. Based on this issue, a hardware and software (HW/SW) co-design approach can obtain maximum performance, and is easily integrated with the other functions to complete the system. This paper presents the multi-standard audio decoder design with hardware/software co-design flow. First we need to...
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