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This paper presents a MP3 / AAC decoder with hardware and software co-design method. In this method, both the flexibility of the software design and the lower power consumption and higher speed of the hardware design are considered. Based on the analysis of algorithm complexity and the compatibility, the Huffman and the IMDCT hardware accelerator module are developed to accelerate the decoding process...
A new design approach of the LDPC decoder based on FPGA Impulse C Programming is proposed. The latest technique of Impulse C programming is used to implement hardware circuit, which is more efficient than the traditional HDL method. The decoder for a family of (3,6) LDPC Codes with 0.5 code rate and the block size of 2500 bits is implemented on Xilinx Virtex2 XC2V2000. When the maximum iteration time...
Free Lossless Audio Codec (FLAC) format is getting more and more popular through the Internet; however, up to now, it is hard to find a decoder chip supporting this kind of format in the market and most of the FLAC decoding systems in software are based on personal computer (PC). In this paper, an embedded FLAC decoder system was designed, and the embedded development platform of ARM920T was built...
This paper presents an FPGA implementation for LDPC codes performance simulation. The goal is for fast evaluation of LDPC code to investigate the error floor. The hardware evaluation platform features by fast simulation speed and high precision. The construction of the platform is described. The critical modules designed in the platform such as LDPC encoder, decoder, and AWGN noise generator are presented...
Recent research has shown that in mobile devices, energy efficiency of the total system does not scale at the same pace with the energy efficiency of the silicon. The reason has been attributed to overheads in software, and in the context of multi-media codecs a new approach has been proposed. In this approach hardware accelerators are scheduled quasi-statically thus decreasing the interfacing overhead...
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