The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
An interpreter reads instructions of the source executable and perform each corresponding operation in turn on a software-maintained version of the old ISA's state. Interpretation has emerged as an important tool with real world applications. Interpretation is always adopted to support instruction set emulation and handle the non-hotspot code in a two-stage dynamic binary translation strategy. An...
Abstract- Dynamic binary translation (DBT) converts codes written for a source instruction set architecture (ISA) into optimized code for a target ISA. DBT has emerged as an important tool with real world applications. Interpretation is always adopted to handle the non hotspot code in a two stage DBT system. An important consideration in such DBT systems is the interpretation overhead. We investigate...
Change original PNG software decode, update decode algorithm, implement hardware Huffman decoder, speed up PNG decode process. This paper discuss the implementation of Huffman decoder in ASIC based on the feature of table and compressed data. The result under the test of EDA tools and Matlab shows the Huffman decoder for PNG decode without distortion.
The paper reports on an attempt to implement a real-time hardware H.264 video decoder. The initial results of the project are presented, especially a customized RISC core and some digital modules, both of which have been implemented in Xilinx FPGA. The former has to serve as a host processor that supervises the latter, which speed up the essential decoding subtasks. The system is designed and tested...
Error correction software for Bose-Chaudhuri-Hochquenghem (BCH) codes is optimized for general purpose processors that do not equip hardware for Galois field arithmetic. The developed software applies parallelization with a table lookup method to reduce the number of iterations, and maximum parallelization under a cache size limitation is sought for a high throughput implementation. Since this method...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.