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We experimentally demonstrate, for the first time, a new metallic carbon nanotube (CNT) removal technique that can be readily scaled to full-wafer-scale. Existing metallic CNT removal techniques either do not remove enough metallic CNTs, or are not VLSI-compatible, or impose very large area costs when applied to wafer-scale VLSI (up to 200%). In contrast, our new technique retains VLSI-compatibility,...
We report on field-effect transistors based on single-crystalline ZnO nanowires with a diameter of about 50 nm grown by wet-chemical synthesis. The as-grown nanowires have a large conductivity that makes it difficult to control the drain current with the gate field, but the conductivity is greatly reduced by a post-growth anneal at 600??C. Using a solution-processed organic gate dielectric with a...
This paper presents a novel design of ternary logic inverters using carbon nanotube FETs (CNTFETs). Multiple-valued logic (MVL) circuits have attracted substantial interest due to the capability of increasing information content per unit area. In the past extensive design techniques for MVL circuits (especially ternary logic inverters) have been proposed for implementation in CMOS technology. In CNTFET...
The authors have recently proposed a new type of gated bilayer graphene-based transistor based on many-body tunneling, for ultra-low power (perhaps 1000 X compared to CMOS) room temperature operation. The physics of this system can be addressed by treating the layer (top and bottom) degree of freedom as a pseudospin, much like spin (up and down) in a ferromagnet. Electrons in one layer of a bilayer...
Latest fabrication technologies of self-assembly nano-circuits (carbon nanotubes, silicon nanowires, etc.) have deployed bottom-up techniques that reach feature sizes well below 65 nm, holding great promise for future large silicon-based integrated circuits. However, new nano-devices intrinsically have much higher failure rates than CMOS-based ones. Thus, new design methodologies must address the...
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