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The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.
A novel DeMOS device with modified body and source region in grounded gate (gg) NMOS configuration for ESD protection is proposed. Detailed 3D simulations indicate a high failure threshold because of moving current filaments and self-protection from gate oxide breakdown, even for fast transients. A detailed physics of second basepushout and moving filaments is discussed.
Adiabatic failures due to an initial peak voltage of VF-TLP measurements were observed at the input gate of a 40 nm CMOS technology. Moreover, a correlation was verified between the failure current of the VF-TLP measurements and failure voltage of CDM testing. Through the transient analyses by a VF-TLP system, the performance of a diode-stack was better than that of SCRs as an input protection for...
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