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The main constraints in recent trends of VLSI technology are power, area and delay. CMOS designs occupy more area and dissipate more power. Power dissipation results in heating up of an IC which directly affects the reliability and performance. Multipliers are the integral part of major application systems like Microprocessor, Digital Signal Processor (DSP) etc., so it is necessary to optimize the...
This paper makes a comparison between various quasi-delay-insensitive (QDI) asynchronous ripple carry adders (RCAs) realized using a delay-insensitive dual-rail code which correspond to 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The QDI RCAs considered are 32-bits in size and correspond to a variety of timing regimes viz. strong-indication, weak-indication, early output,...
As technology advances towards the deep sub-micron regime, energy consumption of digital circuits is becoming more serious. Supply voltage (VDD) scaling is the effective knob to achieve minimum energy consumption. This paper aims at obtaining the minimum energy optimal VDD for the design of Gate Diffusion Input (GDI) logic circuits. A 10 transistor (10T) GDI based full adder circuit is designed for...
This paper presents a novel design of ternary full adder (TFA) using hybrid single-electron transistor (SET) and MOS technology. The proposed circuit is evaluated using the Cadence Spectre simulator with 180nm CMOS technology and SET macro models under various test conditions. Results show that the proposed TFA dramatically reduces the number of transistors required with little or no loss in energy...
In this paper, we propose a 1-bit Full Adder circuit built with Ballistic Deflection Transistors (BDT). BDT is a disruptive technology based on AlGaAs/InGaAs heterostructure. Different combinational circuits were successfully realized using BDT NAND gate and General Purpose Gate (GPG) structures. The developed circuit is an extension of BDT GPG and different from that of the previously implemented...
Memristor technology has tendered the new dimensions in the semiconductor technology as a potential solution to offer high density, low power, non volatile digital logic and memory functions. In this paper nano-device property of Memristor has been utilized to design an area efficient high speed full adder. In comparison to other design of logic gate and full adder, the novel full adder circuit has...
Full adder circuit is one of the most important digital functional block used in ALU. This paper presents a novel design of 8T full adder. The 8T full adder is designed on basis of a new logic 3T XOR and 2:1 multiplexer, in total of 8T. Compared to other existing full adders of 10T, 14T. There is significant improvement in power consumption, delay and power-delay product. For a supply voltage of 1V...
The main requirement of Very Large Scale Integration (VLSI) circuit is to be fast and low energy consumption. So, the analysis is done by optimizing the delay, which results in fast processing and low average energy consumed. A 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 90 nm technology. The results from...
In this paper, a review study and analysis of 1-bit full adder designs is presented with different logic styles such as Hybrid pass logic with static CMOS (HPSC), Hybrid and Hybrid-CMOS. Different styles of logic structures are used to design hybrid-CMOS namely pass transistor logic, complementary pass transistor logic (CPL), swing restoration CPL (SR-CPL) etc. So far the hybrid logic style provides...
In the era of advanced microelectronics, designing an energy efficient processor is a prime concern. Full adder is a most crucial unit in digital signal processing applications. This paper addresses the implementation of 1-bit full adder cell. In addition to this, AND and OR gate as an essential entity is also proposed with minimum hardware overhead. The circuit being studied is implemented using...
This brief proposes an improved XOR logic gate and a novel full adder. The presented XOR has simple structure which consists of 2 CMOS transistors and 4 memristors, and it reduces 4 CMOS transistors compared with the previous. In addition, the novel full adder consists of 7 CMOS transistors and 10 memristors. This novel full adder reduces 8 CMOS transistors and 2 memristors, which means the size of...
The widely using CMOS technology implementing with irreversible logic will hit a scaling limit beyond 2020 and the major limiting factor is increased power dissipation. The irreversible logic is replaced by reversible logic to decrease the power dissipation. The devices implemented with reversible logic gates will have demand for the upcoming future computing technologies as they consumes less power...
Physical limitations for CMOS technology have provided the way for manufacturing the quantum cellular automata technology-based hardware elements at Nano level. From the purpose of very high speed, area and low power consumption, this Nanotechnology has been taken into consideration. Improving their structures will lead promoting the system performance completely, because the Full adders are assumed...
Reversible logic gates are implemented over a high scalein the future technologies. Reversible logic is seen as a demandingfield with variegated applications like CMOS designs consumingless power. This paper proposed design of a full Adder/Subtractorcircuitry with the help of fault tolerant based Reversible logic gates. In the given paper, a full adder/subtractor is proposed with help ofMIG (Modified...
Arithmetic circuits like adder, multiplexer etc. arethe most important circuits in digital signal processing andmany more applications. Full adder circuit is the basic cell ofarithmetic circuits. Many applications require circuits of highthroughput, small area and consume ultra-low power. In thisregards, this paper brings forward a new full adder circuitthat uses 10-Transistors and improved version...
This paper deals with the implementation of low voltage, energy efficient and high speed 1-bit Full Adder (FA) cell in pass transistor (PT) logic by using 20 nm compact model parameters. The existing full adder with pass transistor logic suffers from a drawback of replication of full swing in sum and carry outputs and voltage step existed in both the outputs at low to high transition. These will be...
The advancement in IC technology is primarily attributed to the MOSFET scaling theory. As the transistor size reduced, power consumption also reduced. As the process technology reached nano-meter regime, silicon CMOS started developing Short Channel Effects which led to increased power dissipation. A trade-off arose between power-dissipation and area. Alternatives to CMOS were found to avoid the trade-off...
Full adder cells play a vital role in numerous VLSI circuits. Therefore, design of an energy-efficient full adder which operates reliably in submicron technologies has become a great concern in recent years. Some previously designed cells suffer from non-full swing outputs, high-power consumption and low-speed issues. In this paper, two high-speed, low-power and full-swing full adder circuits are...
This present paper, a 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 180 nm technology. The proposed results are compared with the previous existing designs in terms of power and delay. It is observed that the power consumption is reduced by 65.19 % for three transistor XNOR gate and 48.11% for eight transistor...
Arithmetic logic unit (ALU) is an important part of microprocessor. In digital processor logical and arithmetic operation executes using ALU. In this paper we describes 8-bit ALU using low power 11-transistor full adder (FA) and Gate diffusion input (GDI) based multiplexer. By using FA and multiplexer, we have reduced power and delay of 8-bit ALU as compare to existing design. All design were simulated...
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