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The main objective of this paper is to design the low power consumption and less area occupied combinational circuit here we designed half adder circuit using three different logic styles: CMOS NAND gate logic, CMOS transmission gate logic, and NMOS pass transistor logic. All the circuits are simulated and compared by using Cadence Virtuoso IC 6.1.5, 180nm CMOS Technology with the supply voltage of...
With the increasing complexity of electronic circuits and to meet the demand of high performance, the design and optimization of electronic circuits need to be automated with high degree of reliability and accuracy. In order to optimize hardware requirements of digital combinational circuits, evolutionary and innovative techniques need to be enforced at various levels such as at gate level and device...
The study is mainly intended to solve the problem of Bisha University traditional Combinational Logic Circuits labs in design logic course. This course is one of the prescribed courses in computer science department-semester five. In A set of programmable virtual instruments in the Combinational Logic Circuits (VIs) have been designed and tested Using LabVIEW environment. The aim of this study is...
With the advancement of nanometer scale design technology, transient faults often occur in circuits and thus require low power dissipation design. Reversible logic has become one of the recent emerging research interests contributing to the field of low power dissipating circuit design in the past few years. Few of its application areas include CMOS low power design, quantum computing, network security,...
Recent experiments in the field of VLSI designing and Nanotechnology have demonstrated a working cell suitable for implementing the Quantum-dot Cellular Automata (QCA). QCA is a transistor less computational model which is expected to provide high density nanotechnology implementations of various CMOS circuits. QCA has been constrained by the problem of meta-stable states. QCA adder with comparatively...
The circuits like Logic gates, Adders, Multipliers are the basic building block of the digital circuits. These combinational circuits can be designed by using the concepts of the reversible logic. The reversible logic is either a physically reversible or logically reversible. In this paper the combinational circuits are logically reversible. One of the applications of the reversible logic is Quantum...
Nanomagnetic logic, an emerging nanotechnology has unique features. Circuits designed with NML consume very less power and have the capability to retain the information stored in the absence of power supply due to their inherent magnetic nature. The nature of these circuits is different from CMOS and molecular QCA. They can be better studied by evaluating combinational circuits. A very high speed...
Major proportion of the manufacturing cost of digital circuits is devoted to testing part. Reduction in the number of tests lowers the manufacturing cost and market price of digital circuits. The main focus of this research work is to minimize the number of tests performed to find faults in combinational circuits. The authors framed a new technique comprising of three phases. The first phase identifies...
Reliability analysis of combinational circuits has become imperative these days due to the extensive usage of nanotechnologies in their fabrication. Traditionally, reliability analysis is done using simulation or paper-and-pencil proof methods. But, these techniques do not ensure accurate results and thus may lead to disastrous consequences when dealing with safety critical applications. In this paper,...
In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). While this technique offers great dynamic power savings mainly in array multipliers, due to their regular interconnection scheme, it misses the reduced...
In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low dynamic power consumption...
In this paper, a new self-testing method for combinational circuits backed up with polymorphic gates is presented. Testing feature is completely merged with normal circuit operation where the single stuck at fault model is applied. Experimental results show that our method is able to detect all stuck-at-faults with reduced number of test vectors and insignificant amount of redundancy and high fault...
Since the scalability of logic circuits is becoming larger and more complex, the auto-design is becoming more and more difficult. In order to improve automatic design and performance evaluation of logic circuits in efficiency and capability of optimization, multiobjective simulated annealing (MSA) based increasable evolution approach is designed to evolve logic circuits automatically with an extended...
A new approach to look-up-table (LUT) implementation for memory-based multiplication is presented, where the memory-size is reduced to half at the cost of some increase in combinational circuit complexity. The proposed design offers a saving of nearly 42% area and 38% area-delay product (ADP) at the cost of 6% increase in computational delay for memory-based multiplication of 8-bit inputs with 16-bit...
Variable-latency designs may improve the performance of those circuits in which the worst-case delay paths are infrequently activated. Telescopic units emerged as a scheme to automatically synthesize variable-latency circuits. In this paper, a novel approach is proposed that brings three main contributions with regard to the methods used for telescopic units: first, no multi-cycle timing analysis...
Decimal multiplication is an integral part of financial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area...
Higher operating frequencies may be obtained in digital systems by using wave-pipelining which permits clock frequencies higher that dictated by largest propagation delay between input and output. This, however, requires proper selection of clock periods and clock skews so as to latch the output of combinational logic circuits at the stable periods. In the literature, only trial and error and manual...
Radiation induced transient faults, formerly a concern mainly for memory devices, became one important element contributing to the increase of SER of combinational logic too. Conventional mitigation techniques based on time or space redundancy, either will no longer cope with the long duration transient faults predicted for future technologies, or impose heavy penalties in terms of area, power, and/or...
It is known that fast, fully combinational leading-digit detector circuits can be generated efficiently by recognizing their inherent hierarchical structure. It is shown herein that this structure is not only hierarchical, but also recursive. This recursivity fully defines a minimal-complexity circuit, thus guaranteeing optimal circuit synthesis. Such a circuit having an N-bit operand generates all...
Reliability analysis of digital circuits is becoming an important feature in the design process of nanoscale systems. Understanding the relations between circuit structure and its reliability allows the designer to implement some tradeoffs that can improve the resulting design. This work presents a probabilistic model that computes the reliability of combinational logic circuits relating to single...
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