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Reversible logic is becoming a more and more attractive option to traditional logic, due to its potential to reduce heat dissipation. However traditional circuit design techniques can not always be translated to reversible circuits, and so new techniques for e.g. fault tolerance must be developed. We present a design for a reversible majority voter circuit which has applications not only in the development...
Integrated circuit chips fabricated using nano-scale CMOS technologies will be prone to errors caused by fluctuations in threshold voltage, supply voltage, electromigration, random dopant fluctuations, aging, timing errors and soft errors. Design of nano-scale failure-resistant systems has drawn significant interest in past few years. One common approach to reducing errors is the use of triple modular...
The common design problem in various approaches for self-checking adders is the fault propagation due to carry. Such a fault can misguide the system to detect the particular faulty module. In this paper, we proposed a self-checking Carry Select Adder (CSA) with fault localization ability. Our scheme can provide minimum area overhead for self-recovery process because instead of replacing the whole...
Due to the evolution of technology constraints, especially energy constraints which may lead to heterogeneous multi-cores, and the increasing number of defects, the design of defect-tolerant accelerators for heterogeneous multi-cores may become a major micro-architecture research issue.
This paper presents a concurrent error detection(CED) technique for a bit-slice of a full-adder. The proposed method involves computing the sum and carry bits in two alternative ways so that transient faults will be detected by comparing the results (Sum and Carry out) obtained from the two computing paths. This technique attempts to reduce the amount of extra hardware and cost of the circuit. In...
Modulo 2^n+1 multiplier is one of the critical components in the area of data security applications such as International Data Encryption Algorithm (IDEA), digital signal processing, and fault-tolerant systems that demand high reliability and fault tolerance. Transient faults caused by electrical noise or external interference are resulting in soft errors which should be detected online. The effectiveness...
In this paper we present a new self-checking ALU with duplicated functional outputs. The arithmetic and logic functions as well as their inverses are implemented within a single ALU cell. Two new ALU cells which are intended for different application requirements (e.g. computational speed, hardware overhead and power consumption) are introduced. The hardware overhead for the implementation of the...
This paper presents a novel method of designing embedded checkers for constant weight codes. The design method is based on an operation that maps a binary vector to a vector of half length and half weight. Applied to words of constant weight codes this operation preserves essential properties of these words. The checkers designed with this method have a much smaller size than previously proposed embedded...
As a result of shrinking device dimensions, the occurrence of transient errors is increasing. This causes system reliability to be reduced. Thus, fault-tolerant methods are becoming increasingly important, particularly in safety-critical applications. In this paper a novel fault-tolerant method is proposed through combining time redundancy with information redundancy to reduce hardware complexity...
The testing of LSI chips is expensive and unsatisfactory. On the other hand there are cases (as in space ship computers) where a damaged chip must be localized and replaced. The use of self-checking chips seems to be one of several possible solutions of this problem. The theory of the structure of self-checking logical circuit is covered by literature at least at the fundamental form (see References)...
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