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Compact and high-speed hardware architectures for the 192-bit hash function Tiger are proposed and their gate counts and throughputs are evaluated using a 90-nm CMOS standard cell library. The implementations achieve practical performances of 22.5 K with 2.2 Gbps and 46.4 Kgates with 6.95 Gbps. These throughputs are 1.5-2 times higher than those of the SHA hash family SHA-256/-512, but the hardware...
This paper presents several architectures of circuits destined to the realization of the modular exponentiation operation c = (me) mod n, which is the basic and most time-consuming operation in the cryptographic algorithm RSA. Then, a modification of one of the presented architectures is shown, which was carried out to enable the realization of the exponentiation circuit with current-mode digital...
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