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Square root extraction over GF(2m) is introduced and a new hardware architecture for exponentiation over GF(2m) based on the square root extraction is proposed. Compared with the classical square-and-multiply architecture, the proposed architecture is shown to calculate exponentiation with fewer cycles over GF(2m) in most cases.
Compact and high-speed hardware architectures for the 192-bit hash function Tiger are proposed and their gate counts and throughputs are evaluated using a 90-nm CMOS standard cell library. The implementations achieve practical performances of 22.5 K with 2.2 Gbps and 46.4 Kgates with 6.95 Gbps. These throughputs are 1.5-2 times higher than those of the SHA hash family SHA-256/-512, but the hardware...
This paper deals with the design of an area-time efficient hardware architecture for the multivariate signature scheme, Rainbow. As a part of this architecture, a high-performance hardware optimized variant of the well-known Gaussian elimination over GF(2l) and its efficient implementation is presented. Besides solving LSEs, the architecture is also re-used for the linear transformation operations...
A high performance architecture of elliptic curve scalar multiplication based on the Montgomery ladder method over finite field GF(2m) is proposed. A pseudo-pipelined word serial finite field multiplier with word size w, suitable for the scalar multiplication is also developed. Implemented in hardware, this system performs a scalar multiplication in approximately 6lceilm/wrceil(m-1) clock cycles and...
High data throughput AES hardware architecture is proposed by partitioning the ten rounds into sub-blocks of repeated AES modules. The blocks are separated by intermediate buffers providing a complete ten stages of AES pipeline structure. Furthermore, the AES is internally evenly divided to ten pipeline stages; with the addition feature that the shift rows block (ShiftRow) is structured to operate...
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