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In ultra-scaled technologies, the absence of suitable models for the MOSFET aging mechanisms leads to a lack of understanding of their real impact on the circuit performance and reliability. In this work, models for two of the main reliability issues at device level, bias temperature instability (BTI) and time dependent dielectric breakdown (TDDB), are presented. The models cover important properties...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
Many charge pump structures that overcome gate-oxide overstress have been proposed in the last few years. Though they differ in the number of phases and in efficiency, they have almost the same current driver capability. A new charge pump without gate-oxide overstress, with a better current driver capability is proposed here. The new circuit is derived from a two-phase charge pump in order to inherit...
In the last years the gate-oxide overstress has become a great concern for CMOS circuits and even more so for circuits such as charge pumps. A new charge pump circuit that overcomes the gate-oxide overstress problem and has improved efficiency is proposed in this work. Simulations have shown that for 1??A current load a four-stage structure of proposed circuit reaches efficiency of about 64%, what...
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