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The problem of information storage reliability improvement in random access memory (RAM) devices oriented to application as part of gate arrays designed for space-related application is considered in this article.
This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm containing an estimated 1.4 billion transistors. The core and chip design methodology and specific design features are presented, focusing on techniques...
Reliability of metal-oxide-semiconductor field-effect-transistor (MOSFET) devices is a growing concern as the scaling of these devices is increased. Major contributors to the reliability issues of MOSFET devices include negative bias temperature instability (NBTI) in p-type MOSFET. NBTI phenomena causes threshold voltage shift (increasing Vt) of pMOS devices over time. This results in slow down of...
A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by...
In this work we have demonstrated, for the first time, a 0.605μm2 dual core oxide (DCO) dual Vdd 8T SRAM cell in 45 LPG triple gate oxide CMOS process for use as L1 cache for high performance low leakage mobile applications. The DCO 8T SRAM operates under dual voltage supplies with write assist. Compared to traditional single-end 8T cell, DCO 8T SRAM showed the same performance with only half the...
We present a 46 nm 6F2 buried word-line (bWL) DRAM technology, enabling the smallest cell size of 0.013 mum2 published to date. The TiN/ W buried word-line is built below the Si surface, forming a low resistive interconnect and the metal gate of the array transistors. We demonstrate high array device on-current, small parameter variability, high reliability and small parasitic capacitances, resulting...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
Single, high energy, high LET, ions impacting on a Floating gate array at grazing or near-grazing angles lead to the creation of long traces of FGs with corrupted information. Every time a FG is crossed by a single ion, it experiences a charge loss which permanently degrades the stored information. If the ion crosses more than one FG, the threshold voltage of all those FGs interested by its track...
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