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This paper reports 90nm embedded B4-Flash technology and its superior performance and reliability. Embedded B4-Flash has been implemented to certain 90nm CMOS process and fabricated its 16Mbit test array chip. B4-Flash superiority of high speed program and erase, high reliability has been confirmed by evaluating the 16Mbit test array chip and single bit test vehicle. Direct comparison of the retention...
We introduce implementations of arithmetic operators based on the binary stored-carry-or-borrow (BSCB) representation. Several BSCB arithmetic elements, including full-adder, ripple-carry adder, and carry-lookahead adder are presented, followed by detailed design of an array multiplier. In the latter design, the conventional initial AND matrix is transformed and expressed with a redundant radix-2...
A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by...
In this work we have demonstrated, for the first time, a 0.605μm2 dual core oxide (DCO) dual Vdd 8T SRAM cell in 45 LPG triple gate oxide CMOS process for use as L1 cache for high performance low leakage mobile applications. The DCO 8T SRAM operates under dual voltage supplies with write assist. Compared to traditional single-end 8T cell, DCO 8T SRAM showed the same performance with only half the...
Self-aligned shallow trench isolation recess effect on 42 nm node NAND flash to achieve high performance and good reliability has been studied and demonstrated. As cell STI recess is increased by 23 nm, 29% narrower cell Vth distribution width and 54% less cell Vth shift after 125°C, 2 hours can be obtained. Furthermore, the endurance window is obviously improved ~0.5V as the distance of the active...
Device variability due to sub-wavelength lithography, layout complexity, and random effects is impacting manufacturable design. Defects, aging, and noise must also be accounted for in design and manufacturing. Characterization structures to quantify these effects, measured behaviors, the resulting models, and design and tools mitigation actions are presented in this paper.
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can...
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