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Reliability growth testing allows the manufacturers to identify and eliminate critical failure modes during new product development. Such practices become increasingly difficult to implement in today's fast-paced, decentralized business environment. In addition, a growing number of firms start to bundle the product with the services by offering lifecycle reliability commitment under performance-based...
A number of engineering principles are introduced to the students of undergraduate mechatronics courses that arm them with a valuable tool in design and problem solving. These twenty principles are first introduced to the students and then reinforced during various courses by the use of case studies and projects. Each of the twenty principles is reviewed and examples given where appropriate. An example...
On the basis of the minimum principle of the total cost, using the structure of logistics network and Mixed-integer Non-linear programming, we propose a mathematical model, taking the uncertainty of demand and number of recall and return of goods, the dynamicity of closed-loop network, the environment of E-commerce, and the time value of currency into account. And then we use LINGO to solve the problem,...
In-circuit test (ICT) has been used for more that 30 years to test for correct assembly of components on to a printed circuit board (PCB). The premise behind the in-circuit test philosophy was based on gaining netlevel access to a circuit and driving and sensing signals through the components of that circuit to determine if the components were placed correctly and soldered correctly to the board....
As printed circuit boards are steadily becoming faster, existing test technologies leave significant holes in coverage. In 2007 we presented a new approach to detecting power and ground defects using "network parameter measurements". This paper analyses the effectiveness of this technique in a high volume manufacturing environment.
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Most of the existing built-in self-repair solutions reuse IP-Cores for BIST without modifications. However, this prevents an optimized test and repair interaction. In this paper, the concept of modular BIST for memories is introduced, which supports a more efficient interleaving of...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
This tutorial is directed to all today's and future users of gas insulated substations and transmission lines (GIS and GIL). It gives basic and technical information about the functions, manufacturing, installation, testing and about specifying the right equipment. A special chapter deals with the insulating gas sulfur hexafluoride (SF6), including information about property, handling and recycling...
The increased costs involved in testing new complex devices and the need for rapid processing of information are driving the automation of the electronics test area. This paper presents a plan for the automatic collection and analysis of test information. Case studies are presented of system development and of its applications.
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