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Face recognition systems play a vital role in many applications including surveillance, biometrics and security. In this work, we present a complete real-time face recognition system consisting of a face detection, a recognition and a downsampling module using an FPGA. Our system provides an end-to-end solution for face recognition; it receives video input from a camera, detects the locations of the...
The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this paper, we use OpenCL, an industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs. Our architectural synthesis tool, SOpenCL (Silicon-OpenCL), adapts OpenCL into a novel...
The deblocking filter is more complex than other modules in the H.264 because it is highly adaptive, applied to each boundary of all 4×4 blocks and updated three pixels in each direction. After careful study and analysis of this filter, we have concluded that its complexity lies in the data dependency and in the control module of elementary filters that compose it, but not in the type of these filters...
MPEG is one of the popular standards in image compression. Blocking is the most annoying artifact of encoding/decoding process. In this paper a post-processing deblocking algorithm for MPEG video stream is proposed. This method is based on the correlation of local pixels in block boundary region. It takes two 4×4 adjacent small blocks on both sides of a block boundary as a local processing region...
Currently the market and the academic community have required applications of image and video processing with several real-time constraints. In order to seek an alternative design that allows the rapid development of real time image processing systems this paper proposes an unified hardware architecture for some image filtering algorithms in space domain, such as windowing-based operations, which...
In this work we present a real time video processing framework, which can handle high data throughput rates. Contrary to common digital hardware realizations which use several image line long shift register pipelines for direct calculation of 2D neighborhood operations, we suggest an efficient cyclic image line storage structure by using dual port block RAM buffers, which are available in recent FPGAs...
This paper presents some propositions to reduce consuming memory and increase operational frequency of hardware implementation of JPEG-LS algorithm for real time applications. By enhancement in the algorithm and using fast divider, memory has been reduced by 24%. Also, considering the proposed non-stalling pipeline architecture by using forwarding technique to avoid hazards, circuit frequency has...
Control the data flow between device interfaces, processing blocks and memories in a vision system is complex in hardware implementation. In the research, high-level synthesis tool is used to design, implement and test the vision system within the context of required control, synchronization, and parameterization on a processor based platform. In addition, both HLS tools and HDL were used for the...
The current explosion of digital media creates threats towards the security in multimedia data broadcasting. Watermarking technique becomes a prospective solution to this coercion by means of Intellectual Property Right Protection, Authentication and Integrity Verification of digital media. In this paper we introduce an approach that enables us to develop a low power, real time, reliable and secure...
This paper designs a reconfigurable video MTD IP core, which established in XUP Virtex-II Pro development system platform. The design takes System Generator for the development tool, which is a system-level modeling tool developed by Xilinx Inc, to built a reconfigurable video MTD algorithm in MATLAB/Simulink environment, which is available for the FPGA platform. Then the algorithm is solidified as...
This paper proposes an embedded vision system for real-time moving object tracking using modified mean-shift algorithm for mobile robot application. This design of modified mean-shift algorithm fully utilizing the advanced parallelism of Field Programmable Gate Arrays (FPGA) is capable of processing real-time PAL video of 720*576 at 25 fps. This hardware implementation realizes time-consumed color...
While the computational power of Field Programmable Gate Arrays (FPGA) makes them attractive as code accelerators, the lack of high-level language programming tools is a major obstacle to their wider use. Graphics Processing Units (GPUs), on the other hand, have benefitted from advanced and widely used high-level programming tools. This paper evaluates the performance, throughput and energy of both...
This paper describes an FPGA-based system capable of computing the distance of objects in a scene to two stereo cameras, and use that information to isolate objects in the foreground. For this purpose, four disparity maps are generated in real time, according to different similarity metrics and sweep directions, and then merged into a single foreground-versus-background bitmap. Our main contribution...
In view of the complexity and high cost of image processing system, the real-time image processing system based on SOPC (System-on-a-Programmable-Chip) is proposed in this paper. The embedded Nios II soft-core processor is used to collect and process the image and the algorithm which has the features of simplicity and great data quantity and parallelism is implemented by the hardware in FPGA. By this...
This paper proposes a coarse-to-fine two-level synchronous data acquisition and transmission system for binocular stereo vision, which satisfies strict synchronous requirement of stereo vision.Specifically,this synchronization system design contains: the hardware circuit design based coarse level and the hardware description language (HDL) design based fine level.The former includes synchronization...
Median filter is a non-linear filter used in image processing for impulse noise removal during morphological operations, image enhancement and other image processing operations. It finds its typical application in the situations where edges are to be preserved for higher level operations like segmentation, object recognition etc. Real-time applications, such as video and high speed acquisition cameras...
Scintillation noise artifacts are a part of intensified imagery for both analog and digital sensors. The high intensity flashes are similar to classic “salt” noise although they often are multiple pixels in extent; they can prove very distracting when utilizing intensified imagery under stressful conditions. In stereo intensified vision system, the fact that artifacts occur at different locations...
There is an improvement to the Bicubic interpolation enlargement algorithm based on the hardware parallel processing in this article. Search table method used in this paper has avoided massive cubic and the floating numbers multiply operation. It reduces the computation load greatly. Convolution operation in tow directions, level and vertical, of the 4x4 picture element matrix on FPGA has been realized...
Median filter has good capabilities for reducing a variety kind of random noise, and causes less ambiguity than linear smoothing filters under same processing size. In order to suppress the impulse noise of digital video signal and meet the system's needs of real-time, it is of great significance to do fast filtering of image based on hardware. By analyzing the common 3×3 filtering window's mathematical...
The MMP is an algorithm for image compression which uses the multiscale method of recurrent patterns, based on dictionary. The MMP has compression ratio at the same level of others compression algorithms which are based on transforms, having been detached to images with high frequency, however its execution time has been shown high, by repeated searches of these patterns in dictionaries. In this paper...
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