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The use of hardware description languages to provide digital image processing results is a recent technique that offers a direct connection to reconfigurable hardware implementation. This paper presents a real time system for digital image processing using Verilog hardware description language that can be followed by immediate hardware implementation possibility. The image enhancement algorithms included...
Financial exchanges provide real time data feeds containing trade, order and status information to brokers, traders and other market makers. ITCH is one such market data feed that is disseminated by the NASDAQ exchange. The work presented in this paper describes an FPGA based ITCH feed handler and processing system. The handler, built on the Stone Ridge RDX-11 hardware platform with a combination...
This paper introduces and discusses dependability features of a Telecomm and and Telemetry subsystem designed under a Brazilian Space Program contract. The whole subsystem has been developed in a hardware description language (HDL), targeting anti-fuse programmable once FPGA devices. The discussed features include device redundancy, at hardware level, and several adopted strategies at the HDL level.
One of the newest computational technologies is the high performance heterogeneous computer (HPHC) wherein dissimilar computational devices such as general purpose processors, graphics processors, field programmable gate arrays (FPGAs), etc., are used within a single platform to obtain a computational speedup. Jackson State University has a state-of-art HPHC cluster (an SRC-7), which contains traditional...
The heterogeneous nature of the modern day applications has resulted in widespread use of Multicore SoC architectures. The emerging Network-On-Chip (NoC) interconnect architecture provides an energy-efficient and scalable communication solution for multiple cores, serving as a powerful replacement for traditional bus architectures. The key to the successful realization of such architectures is a flexible,...
This work presents a high-level synthesis methodology that uses the abstract state machines (ASMs) formalism as an intermediate representation (IR). We perform scheduling and allocation on this IR, and generate synthesizable VHDL. We have the following advantages when using ASMs as an IR: 1) it allows the specification of both sequential and parallel computation, 2) it supports an extension of a clean...
This paper designs a reconfigurable video MTD IP core, which established in XUP Virtex-II Pro development system platform. The design takes System Generator for the development tool, which is a system-level modeling tool developed by Xilinx Inc, to built a reconfigurable video MTD algorithm in MATLAB/Simulink environment, which is available for the FPGA platform. Then the algorithm is solidified as...
The technique of orthogonal frequency division multiplexing (OFDM) is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the fast Fourier transform (FFT) and inverse FFT (IFFT) operations are used as the modulation/demodulation in the OFDM systems, and the sizes of FFT/IFFT operations...
This paper proposes an efficient hardware architecture for H.264 integer transform, quantization, inverse quantization and integer transform module (TQ/IQT). The TQ/IQT architecture can be used for intra 16×16, intra 4×4 and inter prediction modes. It was described in VHDL and was validated and prototyped using a Altera Stratix II FPGA. The design operates at a maximum frequency of 270 MHz and achieves...
This paper describes an FPGA-based system capable of computing the distance of objects in a scene to two stereo cameras, and use that information to isolate objects in the foreground. For this purpose, four disparity maps are generated in real time, according to different similarity metrics and sweep directions, and then merged into a single foreground-versus-background bitmap. Our main contribution...
In order to increase the flexibility of control for stepper motor, a pulse generator based on FPGA is proposed in this paper. Draw State transition diagram by analysis the Principle of pulse generator, and realized in FPGA using Very High-speed Integrated Circuit Hardware Description Language (VHDL). The simulate results show that pulse output in FPGA is consistent with the requirements. The module...
This paper proposes a coarse-to-fine two-level synchronous data acquisition and transmission system for binocular stereo vision, which satisfies strict synchronous requirement of stereo vision.Specifically,this synchronization system design contains: the hardware circuit design based coarse level and the hardware description language (HDL) design based fine level.The former includes synchronization...
Advanced Encryption Standard, a federal information processing standard is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However field programmable gate array offers a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the very high speed integrated...
This paper presents mathematical representation of the Running Discrete Fourier Transform (RDFT) and proposes an architecture for selective harmonics device using RDFT. We used `one multiplier and two adders' arithmetic modules. The proposed architecture has been implemented on FPGA using Verilog HDL. Since this implementation consumes lesser area, its Discrete Fourier Transform (DFT) representation...
This paper presents the hardware implementation of fast FIR low pass filter for Electromyogram (EMG) removal from Electrocardiogram (ECG) signal. We designed the architecture having less critical delay then convention FIR design and fast enough to remove EMG from ECG signal. We Proposed branched tree architecture for adder connection to reduce the critical delay. The Proposed architecture has been...
Digital watermarking is the technique used to embed author's credentials, logo or some other information into digital images which can be used in authentications for courtroom evidence, copyright claims and other applications. The objective of this work is to develop a feasible and invisible watermark embedding hardware for the secure digital cameras using LeGall 5/3 (Discrete Wavelet Transform) DWT...
The problems about load control system of combine and its hardware implementation are discussed. The load control system based on intelligent fuzzy control is set up. The controller is simulated on MATLAB/SIMULINK. A hardware implementation about load control system of combine based on VHDL and FPGA is proposed. According to top-down mode, the VHDL modular design of the controller is carried out,...
In a satellite, there exist various communication subsystem like Telecommand, Telemetry and Payload data transfer. Depending on the requirements of a particular system, different modulation techniques are being used. In general, M-PSK modulation techniques are preferable as they are power and bandwidth efficient. The paper presents the digital implementation QPSK & 8-PSK modulators for satellite...
Median filter has good capabilities for reducing a variety kind of random noise, and causes less ambiguity than linear smoothing filters under same processing size. In order to suppress the impulse noise of digital video signal and meet the system's needs of real-time, it is of great significance to do fast filtering of image based on hardware. By analyzing the common 3×3 filtering window's mathematical...
H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a technique for reducing the amount of computations performed by H.264 intra prediction algorithm. For each intra prediction equation, the proposed technique compares the pixels used in this prediction equation. If the pixels used in a prediction equation are equal, this prediction equation is simplified...
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