The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents the proposal of a new front-end readout electronics (RO) architecture for the ALICE Charged-particle Veto detector (CPV) located in PHOton Spectrometer (PHOS), and for the High Momentum particle IDentification detector (HMPID). With the upgrades in hardware typology and proposed new readout scheme in FPGA design, the RO system shall achieve at least five times the speed of the...
The detection and matching of point features play an important role in most of the computer vision algorithms, such as; for 3-D reconstruction and robotics navigation, localization and mapping. Over the last years various detectors and descriptors have been proposed and successfully applied to the different applications. However, the developed detectors are based on computationally intensive algorithms,...
High Energy Physics (HEP∗) experiments around the globe are using sophisticated equipments to record unprecedented amounts of data to discover some of the deepest mysteries of nature. Efficient parallelized frameworks are needed to achieve the scalability and performance requirements of such scientific data analyses. To accelerate data processing capability, many of the HEP experiments globally are...
Stereo image matching is one of the research areas in computer vision. In stereo image matching, technological developments advances from area based matching techniques to the feature based matching techniques. In this paper, we present a Harris corner detection algorithm for stereo image feature matching. This is an intensity based feature matching algorithm and it controls the strong and weak corners...
The floating point arithmetic process is the common operation in numerous processors. The floating point adder process is the complex operation as compared to the multiplication as it consists of latency, area dependent sub operations. The floating point adder is implemented using Leading One Detector (LOD). This technique improves the performance of the adder in terms of area, delay and speed of...
Since a long time, image mosaicing technique was involved in different domains; in order to have much more information about a scene than the individual views of that scene. The basic idea of this technique is to match features between two overlapped images; in order to find a suitable transformation model (Homography matrix), which allows warping images into a single and common reference frame. Different...
This paper aimed to improve MIMO detector's performance in both throughput and cost. Thus, it presents a FPGA architecture implementation for the SQRD detection in a 4 × 4 16-QAM MIMO wireless communication systems. The exploitation of fine-grained parallelism and coarse-grained parallelism strategies are responsible for bettering the performance of the implementation. Besides, this paper proposes...
Trigonometric-related calculations which are widely found in a broad range of applications can be performed by using COordinate Rotation DIgital Computer (CORDIC) algorithm. CORDIC is often utilized in the absence of hardware multiplier since this algorithm requires only addition, subtraction, bit shifting, and lookup table. This paper provides an implementation of conventional CORDIC algorithm with...
We report the implementation of an adaptive spectral sensing algorithm in hardware description language for IR target classification. The synthesized logic performs computation in digital domain between IR test input and a set of prescribed algorithmic weights to extract desired spectral information from targets as well as identifying its class.
A creation of an image mosaic from a sequence of overlapped views is a powerful mean of obtaining a larger view of a scene than the available within a single view. It has been a subject of research for many years, and it has been used in wide range of applications such as satellite imaging and medical imaging. In this paper a general framework for creating a mosaiced image is illustrated, and through...
This paper describes the preliminary design of FPGA based scan generator and Image Grabber System for Scanning Electron Microscope (SEM). The complete System is built around Xilinx Sparten-6 FPGA. Scanning Electron Microscope uses finely focused beam of high energy electrons for forming the image of the sample. The beam is raster scanned across the sample and the intensity information pertaining to...
This paper presents a novel FPGA-based architecture for the Speeded-Up Robust Feature (SURF) extractor. By leveraging the inherent parallelism of the SURF algorithm, we designed a fully pipelined architecture implemented on the FPGA fabric of a Xilinx Zynq-7020 device (XC7Z020CLG484-1). Compared with other high-performing SURF designs in the literature, our implementation achieved the highest frame...
Systems for aerial vehicles have to face tight constraints on weight, space, and energy consumption due to limited payload and energy resources of aircrafts. This leads to the use of optimised, application-specific components.
Many applications require some type of phase detectors to determine the phase relation between synchronous clocks. The European XFEL timing system [1],[2],[3] utilizes numerous phase detectors to monitor and keep clocks and triggers phase stable.
SURF is a well-known scale- and rotation-invariant feature detection algorithm, and it has been widely used for many object tracking algorithms. But it is hard to implement it in real time due to its high computational complexity. In this paper, the hardware architecture of SURF IP was proposed for real time operation. Especially its block memory usage was greatly reduced by partitioning the SURF...
The growth in embedded systems complexity has created the demand for novel tools which allow rapid systems development and facilitate the designer's management of complexity. Especially since systems must incorporate a variety of often contradictory characteristics, achieving design metrics in short development time is an increasing challenge. This paper presents RAPTOR-Design, a framework for System-on-Chip...
A fundamental problem for Cognitive Radios (CR) is spectrum sensing, secondary users need to reliably detect weak primary signals of possibly different types over a targeted wide frequency band in order to identify spectral holes for opportunistic communications. In this paper energy detection technique based on Neyman-Pearson criterion is implemented to detect the presence of deterministic primary...
This paper describes a system for robust optical object recognition based on sophisticated point features which is completely implemented in a medium-size FPGA. All components needed to process image data are integrated in a System-on-Chip, including a special IP core which accelerates the feature detection step of the Speeded-up Robust Features (SURF) algorithm. The task of object recognition is...
The BPSK modulation and demodulation algorithm is designed and implemented of software defined radio (SDR) transceiver system in this paper. The paper uses a Costas loop to achieve carrier synchronization when the BPSK demodulator is designed. And the loop realize the purpose of phase detection using the more accurate and fewer hardware resources occupy arc tangent phase detector. Firstly, the BPSK...
The frequency offset is the main problem of the conventional SDR receiver for demodulation. In order to overcome this drawback, the new methods are applied to improve the conventional Costas loop which is used to extract carrier. Firstly, the integration and accumulator is designed to realize the function of low-pass filter, which takes up fewer hardware resources. Secondly, the more accurate arctangent...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.