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Shorts and opens are the most common type of defects in digital integrated circuits ICs. They can affect interconnect wires connecting gates or transistors inside. Tools targeting the extraction of these potential defects focus only on the inter-gate bridging faults in order to use this information in pattern generation, and no one presents a method to extract potential intra-grate bridging fault,...
Current paper proposes a new hierarchical approach to defect-oriented testing of CMOS circuits. The method is based on critical area extraction for identifying the possible shorted pairs of nets on the basis of the chip layout information, combined with logic-level test pattern generation. The novel contributions of the paper are a new bridging fault simulator and a test pattern generator, which are...
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