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Modern IC designs contain hundreds of millions of transistors and new approaches of multicore chips take place in commercial products. Identifying worst-case voltage drop conditions in every hierarchical module supplied by the power grid is a crucial reliability problem in modern IC design. In this paper we focused our efforts on a complete design flow using innovative results of our recent research...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
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