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This paper addresses the problem of logic diagnosis of System-on-Chip (SoC). We propose a diagnosis approach based on a matching algorithm between a set of predicted failures and the set of failures observed during the test phase. The result of the diagnosis is a ranked list of suspected nets able to explain the observed failures. Experimental results show the diagnosis accuracy of the proposed approach...
With technology scaling, radiation-induced soft error has been a major concern even for mainstream enterprise applications. Since various hardening solutions impose significant costs in performance, area and power consumption, full soft error protection can hardly satisfy the multiple design goals simultaneously. Recent studies have noted that the circuits have partial intrinsic immunity to soft errors...
We present a new methodology for fast and accurate simulation of signal probabilities in sequential logic. It can be used for analyzing soft error effects at the logic level, estimating circuit reliability, and the like. Experimental results for large benchmarks show that signal error probabilities can be estimated over many cycles with high accuracy.
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