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Since integrating memory blocks on-chip becameaffordable, embedded logic analysis has been employed duringpost-silicon validation and debugging. Failing traces obtainedthrough embedded logic analysis can be used to understand functionaldesign errors, a problem that has been studied extensivelyover the past decade. In this paper, we show that post-processingfailing traces using a computational approach,...
Power gating is one of the most effective ways to reduce leakage power by shutting off the idle blocks in a system-on-a-chip. However, a current surge occurs when the gated blocks wake up from sleep mode, causing voltage fluctuations on the power rails, which is called ground bounce effect. In this paper, input vector control method is used to reduce the ground bounce. Genetic algorithm is applied...
Synchronizers play a key role in multi-clock domain systems on chip. Traditionally, improvement of synchronization parameters with scaling has been assumed. In particular, the resolution time constant (tau) has been expected to scale proportionally to the gate delay 'FO4'. Recent measurements, however, have yielded counter-examples showing a degradation of tau with scaling. In this paper we describe...
Multiprocessor systems-on-chip (MPSoCs) are emerging as a popular SoC design platform. However, major challenges arise from nonscaling global wire delay and from the reuse of intellectual properties (IPs) from different vendors to meet tight time-to-market constraints. Designing the appropriate communication fabrics for such heterogeneous systems becomes a challenging task. In this paper, we present...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
Low power consumption is a key requirement in mobile and other embedded applications. Accurate power estimation during design phase is a key enabler for designing a power optimized SoC. Abstracting accurate power models for complex IPs such as embedded memories is a challenging task. At the same time, the complex modules have a large share in total power consumption of an IC. In this paper we analyze...
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