The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As a process technology is scaling, a reliability problem that may cause a failure in the functionality of the digital circuit becomes an important issue in System-on-Chip (SoC) design. This importance leads to the studies on fault diagnosis and tolerance. In this paper, we propose a static and analytical technique for fault diagnosis focused on the digital circuit. Gate level fault analysis is completed...
This paper presents a new type of a more complete system verification method, which combines a high-level verification methodology based on verification methodology manual (VMM) techniques for functional simulation and system-on-a-programmable-chip (SOPC) techniques for board-level verification, effectively improve the adequacy and reliability of verification and validation efficiency. This paper...
Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused design blocks. In this paper, we propose techniques and methodologies that utilize abundant external don't-cares that exist in an SoC environment for block optimization. Our symbolic code-statement reachability analysis can extract...
Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures, gate-oxide wearout, and transient faults are becoming increasingly common. In order to overcome these issues and develop robust design techniques for large-market silicon ICs, it is necessary to rely on accurate failure analysis...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.