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The hot-carrier effect (HCE) in different channel length NMOSFETs is studied in this letter. It is found that the HCE becomes more serious with the channel length decreasing, which results in serious degradations of the threshold voltage and saturation drain current. Moreover, the relationships of the Stress Induced Leakage Current (SILC) degradation versus the threshold voltage and worst substrate...
Design of 700V Lateral MOSFET integrated in a BiCMOS process has been optimized to improve the stability of its on-state characteristics during lifetime stress. This has enabled new generation off-line SMPS ICs with primary side feedback that has much higher level of system integration compared to earlier generation products.
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
Since the very beginning of the flash memory era, the market has been dominated by the floating gate technology. However, as floating gate flash continues along a very steep scaling path, more and more barriers start to appear, limiting further scaling possibilities of the technology. At the same time, other concepts are preparing to take over. This paper concentrates on the prospect of high-k materials...
Extensive reliability characteristics of ultra-short channel CMOS devices with various process conditions were investigated. We found that device scaling down to 0.1??m is possible by optimizing doping profile and oxide thickness. We suggest that hot-carrier induced circuit lifetime (??f/f=10%) is not a major constraint for Leff=0.1??m at 1.5V operating bias.
The device degradation of profiled LDD nMOSFET due to hot-carrier is studied in detail. It was found that the major degradation mechanism of an LDD type of device was spacer-induced degradation. We proposed the profiled LDD structures which exhibited improvement in lifetime under high field stress. The impoved lifetime correlates with increased depth of peak avalanche region below the Si-SiO2 interface,...
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